SOI means silicon on insulator. In SOI technology, the devices are fabricated on a very thin silicon film, the device and the substrate are separated by a buried oxide layer. Because of this kind of structure, the SOI technique has several significant advantages compared to bulk silicon, such as high speed and low power consumption due to the reduced parasitic capacitance. Full dielectric isolation of SOI CMOS device eliminates the occurrence of bulk-Si CMOS device latch-up and SOI full dielectric isolation make SOI technique have superior performances including high integration density, and good anti-radiation properties. SOI technique has been widely applied in many technical fields such as radio-frequency field, high voltage field and anti-radiation field. With the size of the device continuing to shrink, SOI technique will be probably the first choice of Si technology instead of bulk silicon.
According to whether the active body region is depleted, SOI MOS can be classified into partially depleted SOI MOS (PDSOI) and fully depleted SOI MOS (FDSOI). Generally, the top silicon film of fully depleted SOI MOS is thinner resulting in many disadvantages. In one hand, the thin silicon film has high cost, and in the other hand, the threshold voltage of the fully depleted SOI MOS is hard to control. Therefore, the partially depleted SOI MOS is widely used currently.
The active body region of PDSOI is partially depleted, so that the body region is suspended. The charge produced by impact ionization can't be removed rapidly, resulting in floating body effect which is the special characteristic of SOI MOS. As for SOI NMOS, the electrons in the drain region are collided and ionized to produce electron-hole pairs. The holes flow to the body region, and the floating effect of SOI MOS result in the accumulation of the holes in the body region, so as to raise the electric potential of the body region. Therefore, the threshold voltage of SOI NMOS is reduced and the leakage current is increased resulting in the warping displacements of the output characteristic curve IdVd, known as the Kink effect. The Kink effect which has negative effects on the performances and reliabilities of the device and the circuit should be eliminated. The
Kink effects of SOI PMOS device is not so obvious because the electron-hole pairs produced via collision is much less than SOI NMOS due to the lower ionization rate of the holes in SOI PMOS.
In order to resolve the problem of partially depleted SOI MOS, the method of body contact is usually used to connect the “body” to a fixed electric potential such as the source region or the ground. Referring to FIG. 1a-1b, in a traditional T-type gate body-contact structure, the P+ implantation region formed in one side of the T-type gate is connected to the P-type body region under the gate. During the operation of the MOS devices, the carriers accumulated in the body region release via flowing through the P+ channel to reduce body region electric potential. However, there are still some disadvantages in this T-type gate body contact structure, including complex manufacturing process, increased parasitic effect, degraded electric properties and increased device area.
Given the above, there is a need for an improved manufacturing method of SOI MOS device eliminating floating body effects.